The present invention relates to writing data to a nonvolatile memory.
FIG. 1 illustrates the operations performed to program a word of a flash memory. The memory cells are programmed by channel hot electron injection (CHIE). Channel hot electron injection is described, for example, in “Nonvolatile Semiconductor Memory Technology” (edited by W. D. Brown et al., 1998), pages 17–23, incorporated herein by reference.
The memory is programmed by supplying consecutive programming pulses to the memory cells (one pulse is supplied at each iteration of step 160 in FIG. 1), and verifying after each pulse if the programming has succeeded (steps 120, 130). More particularly, at step 110, the memory receives a program command. At step 114, the memory extracts the program address PA and the program data PD from the program command, and the memory loads PA and PD into appropriate registers. PA is the address of the memory word to be written with data PD. The word has 16 memory cells, denoted Q0–Q15 in step 160. Each bit of data PD corresponds to one memory cell. If the bit is 0, the corresponding cell is to be programmed. If the bit is 1, the corresponding cell is to be left unchanged (the cells are presumed to have been erased).
Also at step 114 the memory initializes a pulse count register PC to 0.
At step 120 (“program verify”), the memory word Q0–Q15 is read out of the memory array. At step 130, that word is compared to PD. If the result is “Pass”, i.e. the word Q0–Q15 already has the data PD, then the programming is completed with a PASS indication (step 134). If the comparison fails, the pulse counter PC is checked at step 140. If PC equals some maximum value PCmax (e.g. 255), the programming is terminated with a FAIL indication (step 150). If not, a programming current pulse is supplied to the memory cells corresponding to the 0 bits of the PD value (step 160), the PC counter is incremented (step 170), and control returns to program-verify step 120.
Step 160 involves application of a “super high” voltage to the memory cells being programmed. The super high voltages are voltages exceeding the normal operational voltages used to read the memory. The super high voltages are generated by charge pumps from normal power supply voltages supplied from external sources. The charge pumps are typically located on the same chip as the memory. A charge pump capable of providing a sufficient current drive for simultaneous programming of up to 16 memory cells needs a large area.
To reduce the charge pump current drive requirements, the programming method can be modified as shown in FIG. 2. Step 160 is replaced with steps 160.1, 160.2, 160.3, 160.4 performed sequentially. At each step, at most four memory cells are programmed. The programming is performed on bits (cells) Q0–Q3 at step 160.1, bits Q4–Q7 at step 160.2, bits Q8–Q11 at step 160.3, and bits Q12–Q15 at step 160.4. (The programming involves supplying a programming pulse to the cells corresponding to the 0's in the PD value.) The programming current requirements are reduced, but the programming time is increased.
Another variation is described in U.S. Pat. No. 5,644,531 issued Jul. 1, 1997 to Kuo et al. In that variation, the charge pump can generate sufficient programming current for five memory bits. The memory detects the number of 0's in the high byte of the PD data (the byte corresponding to bits Q0–Q7) and the number of 0's in the low byte (Q8–Q15). If the total number of 0's in the two bytes is at most five, the programming proceeds as in FIG. 1 (all of the 16 bits are programmed simultaneously). If the number of 0's in each of the bytes Q0–Q7 and Q8–Q15 is greater than five, the programming is performed as in FIG. 2. If the number of 0's in byte Q0–Q7 is at most five but the number of 0's in byte Q7–Q15 is greater than five, then the bits Q0–Q7 are programmed simultaneously, but the bits Q8–Q15 are programmed sequentially in groups of four. If the number of 0's in byte Q0–Q7 is greater than five but the number of 0's in byte Q7–Q15 is at most five, then the bits Q0–Q7 are programmed sequentially in groups of four but the bits Q8–Q15 are programmed simultaneously.